ds314-1 (v1.1) december 20, 2004 www.xilinx.com 1 advance product specification ? 2004 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. introduction the xilinx automotive (xa) spar tan?-3 family of field-pro- grammable gate arrays is specifically designed to meet the needs of high volume, cost-sensitive automotive consumer electronic applications. the four-member family offers den- sities ranging from 50,000 to one million system gates, as shown in ta b l e 1 . xa devices are available in both the extended-temperature q-grade (-40 c to +125 c) and industrial i-grade (-40 c to +100 c) and are qualified to the industry-recognized aec-q100 standard. the xa spartan-3 family builds on the success of the earlier xa spartan-iie family by increasing the amount of logic resources, the capacity of internal ram, the total number of i/os, and the overall level of performance as well as by improving clock management functions. numerous enhancements derive from state-of-the-art virtex?-ii tech- nology. these spartan-3 enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, set- ting new standards in the programmable logic industry. because of their exceptionally low cost, spartan-3 fpgas are ideally suited to a wide range of advanced automotive electronics modules and systems ranging from the latest driver assistance and infotainment systems to reconfig- urable instrument clusters and ecu gateways. the spartan-3 family is a superior alternative to mask pro- grammed asics. fpgas avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional asics. also, fp ga programmability permits design upgrades in the field with no hardware replacement necessary, an impo ssibility with asics. features aec-q100 device qualification and full ppap support available in both extended temperature q-grade and i-grade. guaranteed to meet full electrical specification up to t j =-40 c to +125 c. revolutionary 90-nanometer process technology very low cost, high-performance logic solution for high-volume, automotive applications - three power rails: for core (1.2v), i/os (1.2v to 3.0v), and auxiliary purposes (2.5v) selectio? signaling - up to 333 i/o pins - 622 mb/s data transfer rate per i/o - seventeen single-ended signal standards - seven differential signal standards including lvds - termination by digitally controlled impedance - signal swing ranging from 1.14v to 3.45v - double data rate (ddr) support logic resources - abundant logic cells with shift register capability - wide multiplexers - fast look-ahead carry logic - dedicated 18 x 18 multipliers - jtag logic compatible with ieee 1 149.1/1532 selectram? hierarchical memory - up to 432 kbits of total block ram - up to 120 kbits of total distributed ram digital clock manager (up to four dcms) - clock skew elimination - frequency synthesis fully supported by xilinx ise development system - synthesis, mapping, placement and routing microblaze? processor, can, lin, pci, and other cores pb-free packaging options xilinx and all of our productio n partners are qualified to qs-9000, moving to ts16949 in 2005. please refer to the spartan-3 complete data sheet (ds099) for a full product description, ac and dc specifications, and package pinout descriptions. 06 spartan-3 automotive xa fpga family: introduction and ordering ds314-1 (v1.1) december 20, 2004 00 advance product specification r
spartan-3 automotive xa fpga family: introduction and ordering information 2 www.xilinx.com ds314-1 (v1.1) december 20, 2004 advance product specification 6 r . architectural overview the spartan-3 family architecture consists of five funda- mental programmable functional elements: configurable logic blocks (clbs) contain ram-based look-up tables (luts) to implement logic and storage elements that can be used as flip-flops or latches. clbs can be programmed to perform a wide variety of logical functions as well as to store data. input/output blocks (iobs) control the flow of data between the i/o pins and the internal logic of the device. each iob supports bidirectional data flow plus 3-state operation. twenty-four different signal standards, including seven high-performance differential standards, are available as shown in ta bl e 2 . double data-rate (ddr) registers are included. the digitally controlled impedance (dci) feature provides automatic on-chip terminations, simplifying board designs. block ram provides data storage in the form of 18-kbit dual-port blocks. multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product. digital clock manager (dcm) blocks provide self-calibrating, fully digita l solutions for distributing, delaying, multiplying, dividing, and phase shifting clock signals. these elements are organized as shown in figure 1 . a ring of iobs surrounds a regular array of clbs. the xa3s50 has a single column of block ram embedded in the array. those devices ranging from the xa3s200 to the xa3s1000 have two columns of block ram. each column is made up of several 18k-bit ram blocks; each block is associated with a dedicated multiplier. the dcms are positioned at the ends of the block ram columns. the spartan-3 family features a rich network of traces and switches that interconnect all five functional elements, transmitting signals among them. each functional element has an associated switch matrix that permits multiple con- nections to the routing. ta bl e 1 : summary of spartan-3 fpga attributes device system gates logic cells clb array (one clb = four slices) distributed ram (bits 1 ) block ram (bits 1 ) dedicated multipliers dcms maximum user i/o maximum differential i/o pairs rows columns total clbs xa3s50 50k 1,728 16 12 192 12k 72k 4 2 63 56 xa3s200 200k 4,320 24 20 480 30k 216k 12 4 173 76 xa3s400 400k 8,064 32 28 896 56k 288k 16 4 173 76 xa3s1000 1m 17,280 48 40 1,920 120k 432k 24 4 333 149 notes: 1. by convention, one kb is equivalent to 1,024 bits.
spartan-3 automotive xa fpga family: introduction and ordering information ds314-1 (v1.1) december 20, 2004 www.xilinx.com 3 advance product specification r figure 1: spartan-3 family architecture ds099-1_01_102204 notes: 1. the xa3s50 has only the block ram column on the far left.
spartan-3 automotive xa fpga family: introduction and ordering information 4 www.xilinx.com ds314-1 (v1.1) december 20, 2004 advance product specification 6 r configuration spartan-3 fpgas are programmed by loading configuration data into robust static memory cells that collectively control all functional elements and routing resources. before pow- ering on the fpga, configuration data is stored externally in a prom or some other nonvolatile medium either on or off the board. after applying power, the configuration data is written to the fpga using any of five different modes: mas- ter parallel, slave parallel, ma ster serial, slave serial and boundary scan (jtag). the master and slave parallel modes use an 8-bit wide selectmap? port. the recommended memory for storing the configuration data is the low-cost xilinx platform flash prom family, which includes the xcf00s proms for serial configuration and the higher density xcf00p proms for parallel or serial configuration. i/o capabilities the selectio feature of spartan-3 devices supports 17 sin- gle-ended standards and seven differential standards as listed in ta bl e 2 . many standards support the dci feature, which uses integrated terminations to eliminate unwanted signal reflections. ta b l e 3 shows the number of user i/os as well as the number of differential i/o pairs available for each device/package combination. ta bl e 2 : signal standards supported by the spartan-3 family standard category description v cco (v) class symbol dci option single-ended gtl gunning transceiver logic n/a terminated gtl yes plus gtlp yes hstl high-speed transceiver logic 1.5 i hstl_i yes iii hstl_iii yes 1.8 i hstl_i_18 yes ii hstl_ii_18 yes iii hstl_iii_18 yes lvcmos low-voltage cmos 1.2 n/a lvcmos12 no 1.5 n/a lvcmos15 yes 1.8 n/a lvcmos18 yes 2.5 n/a lvcmos25 yes 3.3 n/a lvcmos33 yes lvttl low-voltage transistor-transistor logic 3.3 n/a lvttl no pci peripheral component interconnect 3.0 33 mhz pci33_3 no sstl stub series terminated logic 1.8 n/a sstl18_i yes 2.5 i sstl2_i yes ii sstl2_ii yes differential ldt (ulvds) lightning data transport (hypertransport?) 2.5 n/a ldt_25 no lvds low-voltage differential signaling standard lvds_25 yes bus blvds_25 no extended mode lvdsext_25 yes lvpecl low-voltage positive emitter-coupled logic 2.5 n/a lvpecl_25 no rsds reduced-swing differential signaling 2.5 n/a rsds_25 no
spartan-3 automotive xa fpga family: introduction and ordering information ds314-1 (v1.1) december 20, 2004 www.xilinx.com 5 advance product specification r ordering information spartan-3 fpgas are available in pb-free packaging options for all device/package combinations. the pb-free packages include a special ?g? character in the ordering code. pb-free packaging for additional information on pb-free packaging, see xapp427 : xilinx lead free packages. revision history ta bl e 3 : spartan-3 xa i/o chart device available user i/os and differential (diff) i/o pairs vqg100 pqg208 ftg256 fgg456 user diff user diff user diff user diff xa3s50 63 29 124 56 - - - - xa3s200 63 29 141 62 173 76 - - xa3s400 - - 141 62 173 76 - - xa3s1000------333149 notes: 1. all device options listed in a given package column are pin-compatible. device speed grade package type / number of pins temperature range (t j ) xa3s50 -4 standard performance vq(g)100 100-pin very thin quad flat pack (vqfp) i automotive industrial (?40c to +100c) xa3s200 pq(g)208 208-pin plastic quad flat pack (pqfp) q automotive extended (?40c to +125c) xa3s400 ft(g)256 256-ball fine-pitch thin ball grid array (ftbga) xa3s1000 fg(g)456 456-ball fine-pit ch ball grid array (fbga) date version no. description 10/18/04 1.0 initial xilinx release. 12/20/04 1.1 multiple text edits throughout. xa3s50 -4 pq g 208 q device type speed grade temperature range: q = automotive extended (t j = -40 ? c to +125 ? c) i = automotive industrial (t j = -40 ? c to +100 ? c) package type number of pins pb-free example: ds099-1_02b_100804
spartan-3 automotive xa fpga family: introduction and ordering information 6 www.xilinx.com ds314-1 (v1.1) december 20, 2004 advance product specification 6 r the spartan-3 family data sheet ds099-1 , spartan-3 fpga family: introduction and ordering information (module 1) ds099-2 , spartan-3 fpga family: functional description (module 2) ds099-3 , spartan-3 fpga family: dc and switching characteristics (module 3) ds099-4 , spartan-3 fpga family: pinout descriptions (module 4)
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